Ctype5=0, Ctype2=0, LOC=0, Ctype1=0, Ctype7=0, LOUU=0, Ctype3=0, LoUIS=0, Ctype4=0, Ctype6=0
Cache Level ID register
| Ctype1 | Indicate the type of cache implemented at level 1. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype2 | Indicate the type of cache implemented at level 2. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype3 | Indicate the type of cache implemented at level 3. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype4 | Indicate the type of cache implemented at level 4. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype5 | Indicate the type of cache implemented at level 5. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype6 | Indicate the type of cache implemented at level 6. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| Ctype7 | Indicate the type of cache implemented at level 7. 0 (0): No cache 1 (1): Instruction cache only 2 (10): Data cache only 3 (11): Separate instruction and data caches 4 (100): Unified cache |
| LoUIS | Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. 0 (0): 0 1 (1): 1 2 (10): 2 3 (11): 3 4 (100): 4 5 (101): 5 6 (110): 6 7 (111): 7 |
| LOC | Level of Coherency for the cache hierarchy 0 (0): 0 1 (1): 1 2 (10): 2 3 (11): 3 4 (100): 4 5 (101): 5 6 (110): 6 7 (111): 7 |
| LOUU | Level of Unification Uniprocessor for the cache hierarchy 0 (0): 0 1 (1): 1 2 (10): 2 3 (11): 3 4 (100): 4 5 (101): 5 6 (110): 6 7 (111): 7 |